Synchronization in a system of interconnected units



y 30, 1961 G. P. DARWIN ET AL 2,986,723

SYNCHRONIZATION IN A SYSTEM OF INTERCONNECTED UNITS Filed Feb. 26, 196013 Sheets-Sheet 1 FIG. IA F l6. l8

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SYNCHRONIZATION IN A SYSTEM OF INTERCONNECTED UNITS Filed Feb. 26, 196013 Sheets-Sheet 6 k k il W? l 1 V J\ mm H J J TRANSCEIVER TRANSCEIVERTRANSCEIVER FIG. 65

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ATTORNEY M y 1951 G. P. DARWIN ETAL SYNCHRONIZATION IN A SYSTEM OFINTERCONNECTED UNITS Filed Feb. 26, 1960 13 Sheets-Sheet '7 G. F. DARWINBy R. C. PR/M IN l/E N TORS A TTORNEY y 30, 1961 G. P. DARWIN ETAL2,986,723

SYNCHRONIZATION IN A SYSTEM OF INTERCONNECTED UNITS Filed Feb. 26. 19601a Sheets-Sheet a ER mmszou i n S wo ERWGMQ Q -R V I I NVE/VTORS: $353MNWLYC.NWIT' ATTORNEY y 30, 1951 G. P. DARWIN ET AL 2,986,723

SYNCHRONIZATION IN A SYSTEM OF INTERCONNECTED UNITS Filed Feb. 26, 196013 Sheets-Sheet 9 n A l A 9" f O m 0 Q V N g U u G. F. DARWIN INVENTORS.R C PR/M A 7' TORNE Y May 30, 1961 G. P. DARWIN ET AL SYNCHRONIZATION INA SYSTEM OF INTERCONNECTED UNITS Fi led Feb. 26, 1960 13 Sheets-Sheet 10wm I n N N MM R M m DP. N A P C G M, a R m N E v. W B m vm Wm us wt M y1961 G. P. DARWIN ET AL SYNCHRONIZATION IN A SYSTEM OF INTERCONNECTEDUNITS Filed Feb. 26, 1960 13 Sheets-Sheet 12 Inst 6 2m 3 6t ESE at .fiat uu at Est k w\| NW c. NW A TTORNEV 30, 1961 G. P. DARWIN ET AL2,986,723

SYNCHRONIZATION IN A SYSTEM OF INTERCONNECTED UNITS Filed Feb. 26, 19601:5 Sheets-Sheet 13 PM? E GR DARWIN /NVENTORS- R C. PR/M TORNE) UnitedStates Patent re SYNCHRONIZATION IN A SYSTEM OF' INTERCONNEETED UNITSGeorge P. Darwin, Summit, and Robert C. Prim, Florliam Park, N.J.,assigns to Bell Telephone Laboratories, Incorporated, New York, N.Y., acorporation of New York Filed Feb. 26, 1960, Ser. No. 11,269

15 Claims. (Cl. 340-447) This invention relates to a system ofinterconnected units and has for its general object the establishmentand maintenance of synchronism therein.

Besides having individual functions to perform, the units, which may beconsidered to be positioned at distinct nodes of a complex, requirevarying degrees of coordination depending upon the employment of thesystem. Typically, control information for co-ordinating the units istransmitted by way of channels of communications which may be viewed aslinks interconnecting the various nodes. If the units are to. besynchronized their operations must take place during time intervalswhich have identical durations throughout the system. However, not allof the units will be operative simultaneously. Some of them may have nofunctions to perform during a specified period while others may bedisabled. Under these circumstances there is an uncertainty as to theextent ofv the complex so that if synchronizing signals were constrainedto originate with a fixed unit, conditions could exist under which thesystem would function improperly by being without central co-ordination.Accordingly, one object of the invention is to provide control circuits,identified with respective units, at a multiplicity of nodes so that thesystem of units forming a closed complex, namely, one having each of itsnodes interlinked with at least one other node, will be self-organizingto the end that its constituent units, are all mutually synchronized bya signal originating with one of the control circuits designated aprimary master. The identity of the primary master for a givenorganization of the system depends upon the extent of its closed complexand the ranking of its control circuitry.

During ,the operation of a system it is often desirable to switch unitsin and out of a closed complex, depending upon their particularassignments. Units subjected to this kind of manipulation must besynchronized with respect to the previously operative portion of thecomplex. It is a further object of the invention to enable added unitsof a system to be organized with respect to a synchronizing controlcircuit previously established as a primary master. In some cases thecontrol circuit of a newly added unit will cause the system of theaugmented complex to be organized with respect to it.

Once synchronism has been attained within a given system, disturbancesand disruptions may cause the units at some of the nodes to fall out ofsynchronism.

In particular, the primary master control circuit, or one of the linksleading from it to the node in question, may suffer a casualty.Accordingly, it is a further object of the invention to detect suchdisturbances and disruptions and to reorganize the entire system withthe automatic designation of an alternative primary master con trolcircuit, thus to establish a new condition of syncronism throughout thesystem. If two separate closed complexes result from such a disturbance,each resultant part of the system will be reorganized with respect to aprimary master control circuit within it.

In a narrower c x yn r niza ion is of particular Patented May 30, 19612. importance in pulse code modulation systems where it is referred toas timing. There, distortion-free transmission of code words requiresuniform spacing of message units. In furtherance of this end a commontechnique employed to date has been self-timing at each node of thecomplex by having an incoming message bit energize a local oscillator tocontrol the time intervals of subsequently received bits. Self-timinghas been reasonably adequate where the transmission of message bits hasbeen from one node to another by way of intervening repeaters. It isunsatisfactory when time division switching takes place at nonterminalnodes of the complex because it is then necessary to interleave themessage bits of newly created signals with those already occupying thecommunications channels. This interleaving can be done satisfactorilyonly when the message bits at the various nodes are identically spaced,that is, when the entire system is timed synchronously with a commonfrequency at each node.

Common system timing can, in principle, be effected in two ways: (a) onthe basis of an averaging procedure, and (b by using a master timer in acommand structure. In the former the complex may be considered to be aweb of links over which timing signals originating at various nodesinteract with each other, making the overall timing frequency of thecomplex the average of the individual frequencies of the various timingcircuits. Implementation of this kind of timing difficult because of theinevitable noise disturbances. present in a large system, leading tofrequency instabilityt In the second method of common timing, a mastertimer is selected to direct all units; of the. system over signalchannels that form a tree of links between nodes. Since there. must be'atiming circuit at morethan' one node of the complex in order to. allowfor a failure of any one of them, there, is a possible ambiguity as towhich timer will direct the system by serving as its'primary master.Accordingly, it, is a, further object of the invention to organize apulse code modulation system so that all of its units are synchronizedunambiguously by a single primary master. Once a common timing commandsystem is in operation the primary master timer may cease to function orthere may be an intervening difiiculty between the node of origin of theprimary master signal and anode of reception. Consequently, it. isastill further object of the invention to reorganize a pulsecodemodulation system so that untis which have fallen out of'synchronismwill unambiguously accept a synchronizing signal originating at asubsequently selected primary master the originally selected primarymaster has ceased to function. It is also an object of the invention toreorganize a pulse code modulation system in which the primary mastercontinues to function but with impaired transmission of its signal sothat um'ts out of synchronism will accept the signal originating at theprimary master by way of a. different intermediate node or a differentcommunications link of the system.

The invention is characterized by having, at each of selected nodes. ofthe complex, a Control circuit associated with the unit directingoperations there. Each control circuit generates a signal having twocomponents. The first component is a signature distinctive to the nodeand the second is a timing signal capable of synchronizing the entiresystem. The signatures originating at nodes that aredirectlyinterconnectedby control links aretransmitted and received, thatis, interchanged. At each such node the signature of highest. rank isselected to designate, as synchronizer, the timing signal associatedwith it and to modify the originally generated node signature. Dependingupon the extent of the complex and the arrangement of its control links,the modified signature is in turn selected at another node as being ofhighest rank, causing a control circuit there to recognize the controlcircuit transmitting the modified signature as its immediate master. Inthis way a tree synchronizing authority is established wherein each nodederives its timing signal along'a chain of links wherein a controlcircuit at one node is the primary master for the entire complex, but acontrol circuit at no one node has more than one immediate master, i.e.,one which is but one link away. Of course, for at least one node theprimary and immediate masters will be the same. When a breakdown occursanywhere in the complex, the system clears itself of the influence ofdisruptive elements and reorganizes.

It is evident that one of the signatures received at a particular nodemust point unambiguously to the primary master timing signal and to someone path over which it is received. In general, this requires a minimumof three items of information: (a) the identity of the primary masternode, (b) a measure of the quality of the channel over which its timingsignal is relayed to the particular node, and (c) the identity of aunique immediate master node through which the master timing signal isrelayed. The first item of information is obtained by assigning anindividual and distinctive rank to each node of the complex capable ofserving as a point of origin for a master timing signal. In a completelyself-organizing system this includes every node. Information pointing toa unique immediate masternode is obtained by selecting that one ofhighest rank of those separated by but one link from a particular node.This is done by referring to the distinct identities of the channelsrelaying timing signals or to code signals associated therewith. If thiswere not done, a particular node would not know which to select of amultiplicity of relayed timing signals originating at a primary masternode.

Although in a large subclass of complexes the second information item,namely, that which measures the qual ity of the timing channel, may bedispensed with, it is required in the most general situation in order toinsure arrival at an unambiguous solution of the problem. Moreover, itis always advantageous for the reason that the certainty of the timingof each node of the complex improves with the quality of its incomingtiming information. Hence it is desirable, not only that the variousnodes accept timing information from an unambiguously designated master,but also that, of various alternative channels linking a particular nodewith the master, the particular node shall accept the best one.

It is possible, in principle, to select any of various differentmeasures of timing information quality, to instrument them in variousways and to keep them up-to-date as channel quality changes. In theinterests of simplicity of presentation and of instrumentation themeasure of channel quality adopted in the illustrative embodiment to bedescribed below is simply the distance separating the primary masterfrom the particular node, measured in terms of the number of links thatseparate them. Inasmuch as each intervening node which passes timinginformation along to one or more of its neighbors inevitably introducessome degradation in the quality of this information, the number ofintervening links is, indeed, a measure of the degradation of the timinginformation and hence an inverse measure of channel quality.

The invention provides the identifying information by having thesignature transmitted by each control node consist of three digits,respectively designating the primary master node (digit 1), the distancebetween the master node and the particular node (digit 2), and theidentification of the particular node (digit 3). It is to be noted thatthe term digit is used in its wide sense, since it refers to adesignation which may contain a great number of the numeralsconventionally employed in arithmetic processes. For example. in asystem containing one thousand nodes each digit of the signature couldadopt any value between 1 and 1,000.

When the signature transmitted from one node is received at anothernode, its third digit serves to identify a possible immediate master forthe control circuit at the node of reception. Once received, thisidentification need not be relayed to any other node and it is relegatedto a fourth digit position. Consequently, the signature generated by aparticular control circuit contains four digits of which only the firstthree are transmitted. The digits respectively designate the primarymaster node (digit 1), the distance separating the primary master nodefrom the particular node (digit 2), the identity of the particular node(digit 3), and the immediate master node (digit 4) which is digit 3received from an immediately adjoining node.

When the system is first activated the signature and timing informationat a particular node are self-generated. As a result the digits are,respectively, 1', 0, j and i where j designates the rank of theparticular node. Initially, the self-generated signature (jojj) at eachparticular node is placed in storage by being preset in its register,while its control circuit may be simultaneously receiving the signaturestransmitted from other nodes of the complex. To eliminate confusionduring organization, comparison of incoming and preset signatures isprevented until a substantial number of the nodes have completelyregistered their preset designations. The delay interval requireddepends upon the number of nodes in the complex. When the delay isterminated, an active comparison process begins in which the three-digitsignatures transmitted from immediately adjoining nodes are compared ona digit-bydigit basis with three digits (1, 2, and 4) of the signaturein storage. Whenever the compared portion of the stored signature isgreater than the incoming signature, it is supplanted in the register bythe latter. The comparison process continues until the smallest, i.e.,highest ranking, of the incoming signatures has been entered into theregister. The third incoming digit stored as digit 4 and designating thenode serving as the relay source or immediate master for the timinginformation originating at the primary master node, directs a timingselector causing the timing signal transmitted from the immediate masterto become the timing signal of the particular node. As a result thesystem is self-organized so that the units at each node of the complexoperate in synchronism.

The self-organization of the complex remains unaltered unless thesynchronizing timing signal fails or the received signature which hasselected the timing signal fails or increases. The first event, that is,failure of the timing signal, may result from a failure of the timer atthe primary master node or from an intermediate failure in thetransmission from an adjoining node. By the same token an increase inthe registered signature portends either a failure at the primary masternode or at some intermediate position. This is because the failureproduces a reorganization at intervening nodes with an attendantincrease in transmitted signatures. When the increase takes place thereis no eifect at a particular node unless special alarm means areprovided, since a given control circuit functions by selecting thelowest incoming signature, otherwise allowing an increase to pass byunnoticed.

A timing failure is detected by a timing monitor alarm. When theincoming timing signal selected by the fourth digit of the storedsignature ceases to appear, the delay generator used during theorganization period is set into operation. The register is cleared andpreset to allow a reorganization of the complex after termination of thetransient delay interval.

An increase of the minimum signature stored in the register is detectedby a signature monitor alarm which may be a stepping switch with aninput terminal connection for each adjoining node. The position of thestepping switch is determined from the fourth digit of the storedsignature, thus identifying the immediate master. Only two of the digitsneed to be monitored by the st pping, switch. They are the digit 1identifying the master no e an th igit 2 d gn ing he distance of theparticular node from the master node. By continuously comparing themonitored digits with their counterparts stored in the register, thecondition for an increase of the minimum signature is quickly detectedwhereupon the delay generator activated previously is set intooperation, commencing the process that leads tosystemrresynchronization.

The kind of synchronization contemplated by the invention isapplicableregardless of the kinds of communications channelsinterlinking the nodes of the complex or whether they extend over greator negligible electrical distances. However, for the purpose ofeliminating collateral considerations, such as those associated withchannel imperfections, the invention is hereafter largely discussed interms of a system whose control signals are transmitted over identical,ideal channels with infinitesirnal command propagation times from nodeto node.

Many techniques for implementing the objects recited above will beapparent after a consideration of a few preferred embodiments of theinvention, taken in conjunction with the drawings, in which:

Figs. lA-lC are schematic diagrams of various complexes whose nodes areinterconnected by channels of communications called links; v

Figs. 2A-2C are schematic diagrams illustrating the self-organization ofa system whose constituent units are at distinct positions of a nodalcomplex;

Figs. 3A-3B are schematic diagrams illustrating the self-reorganizationof the complexes of Figs. 2A-2C;

Fig. 4 is a block diagram of a control circuit at each node of thecomplexes of Figs. 2A-2C illustrative of self-organization at aparticular node of the system;

Fig. 5 is a block diagram similar to that of Fig. 4 supplemented byalarm circuits which respond to disturbances in system synchronizationand illustrative of self-reorganization at a particular node of thesystem;

Figs. 6A-6H, taken together as indicated in the key, Fig. 7, is acircuit diagram of a complete control circuit; and

Fig. 8 is a circuit diagram of the comparator employed for each digitprocessed in the circuit of Figs. 6A-6H.

The invention is best understood by beginning with a consideration ofthe complex in 'Fig. 1A showing a general system and its subordinatecomplexes. The nodes indicated by small circles representunitscontaining control and operational circuitry. These nodes areinterconnected by communications channels marked by solid line links.There is an additional node of the operating complex identified by an x.The channels of communications interconnected it with other nodes of thecomplex are identified by dashed lines. It does not have any controlcircuitry and must rely on self-timing for its synchronization. Afurther node of the complex marked by a small rectangle and connected toother nodes by dot-and-dash links contains control circuitry alone. It

provides an alternative way of transmitting control signals. Fig. 1Aindicates that the operating complex with operating circuitryand thecontrol complex with control circuitry need not be coextensive.

In the control complex of Fig. 1B the nodes of the complex designated bysmall circles are numbered sequentially in accordance with a scale ofprecedence which, as a practical matter, may be determined on the basisof the stability of the timing oscillators positioned at each nodethough, from the standpoint of the present invention, it is arbitrary. Alink symbolized by a solid line interconnects each pair of nodes. Itprovides a two-way channel of communications over which signaturesgenerated by the control circuits at the Various'nodes can be passed inboth directions. Assuming that a minimum numeric designation indicateshighest rank, e.g., greatest stability, the oscillator at node 1 is theprimary master tor the, entire system and the control circuits at allother nodes derive their synchronization signals directly from it.

When a system becomes very large, it is neither practical nor necessaryto provide a direct communications link between each node and everyother node. Rather, the arrangement of Fig. 1C may be used in which eachnode is connected with but two adjoining ones, thus providingalternative transmission paths. Assuming that the oscillator at node 1is the primary master, it can no longer transmit its message directly tonode 4. It must rely on retransmission either from node 2 or from node3. According to the invention, the control circuit at the node with thehigher rank, that is with lower numeric designation, takes precedenceand becomes the immediate master for node 4 whose oscillator isaccordingly synchronized by a signal originating at node 1 and'relayedthrough the immediate master node 2. The alternate transmission path byway of node "3 goes into effect in the event of a casualty at node 2.

To illustrate how the units of a system are initially organized torender the entire system synchronous, reference is made to Fig. ZAshowing serially numbered nodes having a master oscillator at each oneaccorded the priority indicated by its numeric rank. The links betweennodes are shown dashed to indicate that initially no synchronizingchannels have been established before the system is activated. Asdiscussed previously, in the absence of a signal from an adjoining nodethere is generated at each particular node a signature distinctive toit. Since the positions of the constituent digits respectively indicatethe primary master node (digit '1), the distance between the master nodeand the particular node (digit 2), the particular node (digit 3), andthe immediate master node (digit 4), the initial signature at each nodemust be in the form (jojj) where j is the numeric rank of the particularnode. This follows because initially the oscillator at each node is itsown primary master and its own immediate master and clearly does notreceive its signature from any other source. For example, the signatureof node 6 is (6066). Other node signatures are shown in parentheses inFig. 2A beside the numeric designations of particular nodes. -As theself-organization of the system proceedsthe first three digits of everynodes signature are transmittedto each adjoining node and compared withthe first, second and fourth digits there registered. On theunderstanding that, in the present illustration, distance is measured interms of the number of links that separate the particular node from theprimary master, each received signature has its second place digitaugmented by unity to account for the additional link then separating agiven node of origin and a given node of reception. For example, at node4 the signatures compared are 111) from node 1, (212) from node 2, and(313) from node 3. These signatures are compared with the self-generatedsignature at node 4, namely, (404), whereupon the control circuitassociated with the oscillator at node 4 decides that the signalemanating from node 1 is of the highest order and the signature at node4 is modified accordingly by having the digit identifying itinterspersed between the second and third digits of the signaturereceived from node 1 so that the new signature at node 4 becomes (1141).The transient signatures associated with the other nodes of the complexare indicated in Fig. 2B. It is to be noted that the transient signatureat node 8 is (2182). The control circuit at node 8 must choose betweennodes 2 and 5 in selecting its immediate master. It chooses the formerbecause of its lower rank. However, the signature (1121) at node 2cannot be propagated to node 8 immediately, and during the transientperiod the control circuit at node 8 instead recognizes the earliersignature (202) which is modified on reception to (2182). In likefashion node 5 is of higher rank than any of its immediate neighbors,nodes 6, 7 and 8, so that its signatureduring the transient period istheself-signature (5055). The tree of synchronizing authority isestablished as indicated by the solid line links interconnecting thenodes of the complex in Fig. 2B. The arrows attached to these linksindicate the direction of propagation of the synchronizing signals. Atsome time during the transient period the organized control circuitsbegin transmitting their new signatures to their neighbors. When thishappens, as shown in Fig. 2C, the control circuit at anode 2 relays thedigits 112 which become the signature (1282) at node 8. In a-sirnilarfashion the modified signature at node 6, namely, (116), is recognizedat node as (126) which is smaller than (505) so that the final signaturethere be comes (1256).

A self-reorganization of the system takes place whenever the timingsignal originating at the primary master node fails. Assuming casualtyto nodes 1 and 2, the complex of Fig. 2A initially enters its clearingcondition as illustrated in Fig. 3A. Those nodes at which synchronizingsignals are nolonger received from an immediate master node, namely, 3,4, 6, 7 and 8, quickly return to an autonomous state and their controlcircuits produce self-generated signatures. Node 5 continues torecognize node 6 as its immediate master and selects its timing signalaccordingly. It is because all nodes are not cleared immediately that adelay period is necessary in the reorganization as well as theorganization of the system. During the clearing period the controlcircuit at each node of the complex registers its self-generatedsignature as shown in Fig. 3B, thus allowing the reorganization tocommence as indicated in Fig. 3C on termination of the delay interval.Circuits at nodes 4 and 6 accept the signature originating with node 3while circuits at nodes 7 and 8 look to node 5 in seeking an immediatemaster. By the end of the first portion of the transient period node 5has acknowledged node 6 as its immediate master as shown in Fig. 3D buthas not yet had an opportunity to relay the primary master signaloriginating with node 3 to its slave nodes 7 and 8. At the end of thetransient period the reorganization is complete as portrayed in Fig. 3E.If in Fig. 2C only the timing signal relayed from node 1 by way of node6 were affected by having the relay transmission from node 6 to node 5fail, the control circuit at node 5 continues to recognize node 1 as theprimary master, but it chooses node 7 as its immediate master so thatthe final signature at node 5 becomes (1257). Node 7 is preferred overnode 8, since the relayed signature from the latter, (138), is largerthan (127).

The apparatus at a particular node, such as 8, for carrying out theself-organization described in conjunc tion with Figs. 2A2C is shown inblock diagram form in Fig. 4. As in Figs. 2A-2C, the control circuitillustrated is intended for a node having linkages with but nodes 2 and5 of the complex, only two transceivers, 11--2 and 11--5, are needed,one for each linkage. At each transceiver 11 the received control signalfrom an adjoining node contains supervisory and timing information,carried by respective supervisory and timing channels 13 and 14. Thetiming information at both transceivers 11 is routed directly to acontrol timing selector 18. Pending selection of one of the timing leads21, local operations are directed by a local clock 22. On the otherhand, the three-digit signature of the supervisory information issubjected to a comparison process. Before this can take place there mustbe a signature in storage in the storage register 25. At thecommencement of the organization process a start pulse closes a praetgate 27 cansing the register 25 to store the self-signature (8088)produced by the preset generator 28.

Turn now in Fig. 4 to the incoming signatures (mn2) and (p115) on thesupervisory channels 1'32 and 13-5 respectively linking nodes 2 and 5.If the second digits n and q of the incoming signatures represent thedistance 'unit separation between an immediate master and the node 8 ofthe instant control circuit. This is accomplished, for the signaturefrom each adjoining node, in a translator 40 which passes the incomingsignatures to a scanner 45. At the scanner 45 the signaturessuccessively sampled and applied in the form (D D D to a controlcomparator 50 in which a signature already stored in the register 25 iscompared with that sampled by the scanner 45.

Whenever an incoming signature is of higher rank than the comparedportion of that previously set in the register 25, the comparator gate60 is closed, and a newsignature is in turn stored in the register. Onlythe first, second and fourth of the four digits, D D D stored in theregister 25 participate in the comparison process inasmuch as the thirddigit D designates the rank of the local node and the receivedsignatures themselves have but three digits. The fourth digit D of thesignature operates the control timingselector 18 and causes it to makecontact with the appropriate one of the timing leads 21. During thetransient period before the adjoi i g nodes 2 and 5 have been enslavedto their masters, their control circuits transmit the self-signatures(mn2=202) and (pq5=505) which are converted to (212) and (515) by thetranslator 40 at node 8. Assuming the signature transmitted from node 5is sampled first by the scanner, the comparator detects that (515) issmaller than (808) producing a pulse that closes the comparator gate 60.This scanned signature is read into the storage register 25 causing thenode signature to be modified from (8088) to (5185). When the signaturedispatched by node 2 is sampled, the comparator 50 notes that (212) issmaller than (515) and the stored signature becomes (2182), or thetransient signature at node 8 shown in Fig. 2B. After the controlcircuits at nodes 2 and 5 become enslaved to the primary master at node1, their relayed signatures are (122) and Being the smallest of thesubsequently compared signatures, (122) is entered into the register 25where it reads (1282), the final signature of node 8 in the organizedcomplex of Fig. 2C. The fourth digit, 2, in turn directs the timingselector 18 to select the timing lead 21-2 associated with thetransceiver 112 obtaining a timing signal from node 2 and the localtiming is prescribed accordingly.

The first three digits D D D of the stored signature are relayed alongwith the timing signal selected by the fourth digit D to adjoining nodesthrough the transceivers 11. The means for doing this are omitted in theinterest of diagram clarity.

By way of explaining the reorganization of the system when it is in analarm state, the block diagram of Fig. 4 has been supplemented as shownin Fig. 5 with certain of the original blocks of Fig. 4 shown only inoutline form. As noted earlier there are two conditions under which thesystem must reorganize. Both of these stem from a timing failure whichmay originate either at the primary master node or at an intermediatenode.

A failure at the primary master is evidenced by an increase of thesignature of the immediate master node relaying the timing signal. Thisis a consequence of the return to an autonomous state of an immediatemaster when the primary master has failed. If there were no method ofdetecting this increase the comparator 50 would continue to accept thesignature stored in the register 25 as being of highest rank.Consequently, the timing selector 18 would continue to select thesynchronizing signal from a previously established immediate master. Infact, however, proper synchronization of the system might require thedesignation of a difierent immediate master. This is made possible byproviding a signature monitor alarm 82 which operates in the manner of astepping switch. It is directed to select the input line 84 responsiblefor the signature stored in the register 25 as of a given instant. Theselection is easily made by having the fourth digit D in the register 25operate a signature selector 83 that is similar to that of the controltiming selector 18. The first two digits D and D of the incominhibitgate 72 between the control comparator 50 and the register 25. The delayinterval introduced by the delay generator .70 endures sufliciently longto allow all disabled -units of the system to clear themselves ofsignatures no longer valid. During the delay interval the alarm pulsecloses the preset gate 27, enabling the self-signature of the presetgenerator 28 to return to storage in the register 25. Termination of thealarm pulse restores the path through the inhibit gate 72 and allows thereorganization 'process to commence.

The second kind of timing failure may originate at the primary masternode or at some intermediate position. A supervisory signal maycontinue'to be. received, with its signature designating a particulartiming line 21, but

if there is no signal on'the selected timing line, synchronization atthe-particular node and at all other'nodeschoos ing itias an immediatemaster will be disrupted. The 'tiiningfailur'e may be at an intermediatenode which may receive the originally transmitted timing signal from theprimary master without errorbut failto make a retransmission. Or it maybe in one of the channels. Regardless of how the failure occurs, it isdetected by a timing monitor alarm 93 which has a timing alarm generator94 for "each transceiver 11. The fourth digitD, stored in the register25 is used to direct the alarm timing selector 95 to select from amongthe alarm leads 96 that one connected to the transceiver 1'1 monitoringthe signature in storage. When the selected timing signal ceases toappear the delay generator 70 is once again activated causing thecontrol circuit to return to its autonomous state in the fashiondiscussed above. i

The complete control circuit at each particular node necessary to effectself-organization and self-reorganization of a pulse code modulationsystem is shown in Figs.

6A 6H. Separate transceivers 11 (Figs. 6A-6B) are "provided to handleinformation dispatched to and repractice, the three kinds of informationaccommodated by these channels may be coded so that either a singlechannel or a double channel will sufiice.

A typical message channel 12-1 (Fig. 6A) carries conventionalPCM messagecode words which originate locally or are received from some other unitof the system. In either case the message code Words are" handled by adata input-output center 17-1 whose operations are ceived signaturescontain but three digits in binary code. To facilitate identification,each digit maybe modulated by a carrier signal with a distinctivefrequency or it may be prefaced by a pro-established codeword.

The information carried by each timing channel 14 (Figs. 6A-6B) is inthe form of equally spaced pulses or a carrier signal derived from astabilized oscillator. The timing signals received by the varioustransceivers 11 are relayed by respective timing leads 21 to a controltiming selector 18 (Fig. 6D) whose connection to a particular leaddepends upon the fourth digit D of the signature in the storage register25 (Fig. 6F). The selected timing signal is carried directly by a timingoutput load 19 (Fig. 6D) to the data input-output centers 17 to efiectlocal synchronization. The control timing selector 18 is, in effect, aswitch with an individual tongue 20 for each of the timing leads 21. Anappropriate switch is a "relaytree of the :kind shownonpage 308 of lln:

.ofSwitchingfCi'rcuits? .by Keister, Ritchie, and Washburn ;(:VanNostrand, 195.1). Such arelay' tree is. energized .by'signals carriedbya control bundle 23 having aszmany rleadsas there are bitslinthe-digit D stored in the reg- .iste'r :25. and doing the, selecting.Depending upon the abinary sequence of pulses applied, asparticul'arrelay: is activated causingone of the tongues 20 to close; Forye'x-.ample, if the fourth digit in storage is 5, signifying"that :theincoming timing ysignal relayed frommr originating at node 5 is to beselected todir'ectlocal-timingathre'e.

leads of the control bundle. 23, interconnecting the. coh- 1trol timingselector 18.and that portion of the register '25 containing the fourthsdigit in storage, would respec- -tively containnsignals-inthe. sequence@101 which is the binary equivalent of 5. This; combination of signalsisable to energize only the relaycontrolling the 'tong'ue ac-:5 associatedwith the timing lead connectedato athe transceiver receiving the timingsignaloriginating at node .20 '5 and the timing output signal isprescribed accordingly.

.One of the timing leads 21 is connected directly toia local clock 22which is a ima'sterioscillaton.. Whenever' Tithe fourth digitoftheisto'rage register prescribes tha tithe .rlocal controlzcircuitt isto: be the master for'the system, 25 that t0ngue 220+j of the switchassociatedwith'the local ..clqck.22i;=is.activated. Regardless-ref itsorigin, the tim-- ingi's'ignal selected by. the controltiming selector18 be-.

comes identified with the local controlcircuit and it is relayed to eachadjoining nodelhrough the output leads 301-24 (Figs. 6A-6B)uasso'ciatedwith the timing channels a'ofthe .various transceivers. The timingal'armmechanism 10f the timing channel will be discussed subsequently whensystem reorganization is considered. r Turn now to atypical'snpervisorygchannel 13"1 (Fig. 6A). The incoming signature thereon isprocessed in Ia reception" converter 30 in order to transform the seriescoding of digit bits in time sequence to parallel coding that makes the.constituent bits of the digits D D and D simultaneously available onseparate leads in bundles 31 thereof. Whenthe digits have carriers ofdifferentfrelquencies, they are separated by appropriately tunedbandpassfilters 32, one for each digit, and demodulated by respective detectors33. Then the bits of aselected digit, e.g.; D are read into acoderegister 34. As soon as the register-'34 is occupied with a codesequence indicating.

athat a subsequently received bit marksthe commencement of adigit D aclock timing circuit 35 is activated. This causes-a stepping'switch 36tied to an incoming line for each digit to make contact with successiveleads of {a converter register 37 from which parallel readout of each-digit is made. If-the digits are not received simultaneously-{it isnecessary to have a separate code register 34 for each along withsupplementary gating to allow readout of the converter registers 37 onlywhen they are all '55 i occupied. a The implementation of the receptionconverter components is Well known in the computer and telephone arts.In the absence 'of an alarm condition the three digits :of the incomingsignature pass to a translator 40 (Fig. 6C) through a supervisory gate42 (Fig. 6A) which opens onlyiin the event a disturbance is sensed byits associated transceiver 11. Assume that-the digits D D and Denteringa particular translator 40--1 have the values t, u and v,respectively. 'I'he translator passes t and v without change, but itrelegates 'v' to a fourth place position of digit D -to account for thereservation of the third digit position toi'ndicate the rank of thelocal node. As far as the-bits of the digits themselves are concerned,only thoseassociated with u or digit D are altered. Since the seconddigit represents the distance between a particu- 7 lat node and theprimary master node, it must be augmented by unity to account for thefact that the local node is one link beyond each adjoining node. Theunit addition is made by a conventional binary adde 41 as is well knownin the art.

'15 The output digits D D and D, from the translators are sent byrespective bundles 43 of leads to a scanner 45 (Fig. 6E) having a rotaryswitch 46 for each digit. lhejrotatable wipers 47 of the'switches haveas many ganged blades as the digit scanned contains bits. The wipers 47for the three digits rotate in unison allowing the-entire incomingsignature from a control circuit at an adjoining node to be sampledsimultaneously. The signature is conveyed by separate bundles 48 ofconduc for the respective digits to a control comparator 50 (Fig. .6G)made up of constituent comparators 51, one :for'each digit. Within eachconstituent comparator 51 -there are two sets of relays. The first sethas as many elements as there are bits in the scanned digit. The -sccond set is connectedtothe appropriate one of bundles 26 of leadsinterconnecting the output of the storage register 25 (Fig. 6F) and theinput of the control comparator -50, (Fig. 6G). Depending upon how thedigits being :compared energized their relays, a signal will appear on.one of the three output leads of each constituent com- .paratorSl. Ifthe digits are equal corresponding ones of :the. relays will functionand the signal appears on 'anequivalence lead 54. When the digit scannedis less .than that in storage the. comparator signal is available .onlyon the command lead 55. The condition for which thescanned digit isgreater than that in storage is of noiimportance and the output lead 56so responding is unconnected. Atypical constituent comparator 51-D isshown in moredetail in Fig. 8.

According to the invention, when the scanned signa- 1111 6 is less thanits stored counterpart, it should replace -.the latter in the register25. When this condition is detected by the control comparator 50, acomparator gate 60 (Fig. 6G) is actuated allowing the scanneclsigna-.ture to pass directly into storage through normally open relays of aswitch gate 61 in the paths of the bundles .62 of leads interconnectingthe control comparator 50 and the storage register 25.

The control comparator gate 60 functions on a digitby-digit basisthrough the use of two subordinate. AND gates 63 and 64 andonesubordinate OR gate.65. These gates may be formed from relays in thefashion described on page 37 of Keister et al., supra. If scanned digitD is less than digit D in storage, the signal on the command lead 55-Dfor digit D causes the comparator OR gate 65 to close the normally openrelays of the switch gate 61 to achieve a direct replacement of three ofthe stored digits D D D; by the incoming signature. If the scanned digitD is equal to the digit D in storage, ,thetsignal on the equivalencelead 54D for digit D; is applied to a first terminal of a two-digit ANDgate 63, and if, simultaneously, the second digit D of the incomingsignature is less than the second digit D in storage, the signal on theequivalence lead 55-D for digit D is applied to the second terminal ofthe two-digit AND gate 63, which then closes the previously describedcomparator OR gate 65. A replacement of three of the stored digits alsotakes place when scanned and stored digits D and D are equal, butscanned digit D is less than that in storage. The equivalence leads 54-Dand 54-D for digits D and D along with the command lead 55-D for digit Doperate a three-digit AND gate 64 which once again causes the comparatorOR gate 65 and the switch gate 61 to close.

The register 25 (Fig. 6F) where the complete fourdigit signature of thelocal control circuit is stored is made up of locking relay registerelements of the kind shown on page 449 of Keister et al., supra. Onesuch element is provided for each bit to be placed in storage. Forconvenience the bits of a particular digit are compartmentalized tosimplify lead arrangements. Signals propagated along various bundles 29of incoming leads energize associated relay windings to institute theholding :action of a locking ground. The relays return to normal whenthe ground contact is disrupted. The design and operation of this kindof register is well known in the art.

12 The comparison process requires reference digits in the storageregister 25. These are provided by a preset generator 28 (Fig. 6H) whosecontacts are adjustedto produce the self-signaturev of the local node.When enters the register 25 (Fig. 6F) through the closure,.b'y a pulseoriginating with a delay generator .70, of normally open switches of apreset gate 27 containing one 'set of relays for each digit. The delaygenerator70.re-

instability that would result from having incoming signatures enter theregister during the period Whenit is being set with its self-signature,the delay generator .70 opens the normally closed switchesof aninhibitgate72 conthe previously described switch gate 61 (Fig. 6G).

.; :Digits D D and D in the storage register 25..(Fig

6F). .form the signature transmitted from the particular node to eachadjoining node. The transmittedsignature is relayed by respectivebundles 74 ofleads to a transmission converter 75. (Fig. 6D) whichperforms the inverse function of the reception converter 30 .bypreparing the parallel coded bits for serial transmission to othernodes. There is a register 76for each outgoing digit with a section7730f relays generating the identifying prefix code, A converterstepping switch 78 is driven by the, pulses emitted from a local clocktiming source 79 so that successively sampled bits in storage appear intime sequence at associated modulators 80 where each outgoing digit isgiven a distinctive frequency preparatory to transmission of theoutgoing signature to adjoining nodes. Converter output leads 81 conveythe signature to a transmitter 16 for each supervisory channel, astypified by the channel 13-1 in' Fig. 6A. It does not mat- :ter thatunder some circumstances the stepping switch may begin to functionwithout having read out the entire prefix code since a receptionconverter at an adjoining node will not respond to a transmittedsignature until its code register is energized.

Consequently, once the manual start pulse is applied at a particularnode to read a preset self-signature into 'storage, subsequently acontinual comparison process takes place so that the control circuit atthe node selects that one of the incoming signatures which is less thanthe corresponding digits of its own signature in storage and modifiesthe node signature and the timing of local operations accordingly. Alike process occurs throughout the system, causing it to becomeself-synchronized with respect to a timing signal originating with anunambiguously selected master node.

The system must be reorganized in the event of a system disturbance ofthe kind discussed in conjunction with the block diagram of Fig. 5. Thesignature monitor alarm 82 (Fig. 6F) detects an increase of the incomingsignature responsible for that present in the storage register 25. A.signature selector 83 of the kind used in the timingselector 18 (Fig.6D), with tongues 86 and controlled by the leads of the selector bundle85, is employed for digits D and D of an incoming signature. Pairedbundles 84 of leads handling those digits are connected to eachtranslator and the preset generator 27 (Fig. 6H). The bundles 84-j ofleads to the preset generator 27 are needed only to prevent ambiguitywhere the self-generated signature is stored in the register 25. In thatcase the fourth digit D of the stored signature could as well direct theselector, by means of signals on the selector bundle 85, to anunconnected terminal of the selector 83 sinceit is not possible for thepreset signature to change its value. The respective outputs 87 arecompared with corresponding outputs 88 of the storage register 25 in analarm comparator 89 whose constituent components 90 are of the kindemployed in the control comparator 50 (Fig. 6G). The associated AND andOR 13 gates 91 and 92 (Fig. 6H) operate in the manner described for thecomparator gate 60 (Fig. 66). If the selected incoming d gi D is greaterthan that in the register 25 the resulting output pulse of the alarmcomparator 89 activates a first OR gate 92 which in turn activates asecond OR gate 71 causing the delay generator 70 to function. Should thefirst digits be equal but the second selected incoming digit D begreater than that .of the second digit D in storage, the resultingoutput pulses are applied to an AND gate 91 and an OR gate 92, in turn,once again causing the delay generator 70 to begin its operating cycle.

Reorganization of the system is also necessary if the signal on thetiming channel 14 fails. This is achieved by a timing monitor alarm.There is a timing alarmgenerator 94 (Fig. 6A) of the relay variety ineach timing channel 14. It responds only when no timing signal isreceived. Generally, the timing signal is a train of equally spacedpulses, and the alarm generator 94 may be a normally closed relay with atime delay lasting beyond the anticipated separation interval of timingwave pulses. The pulse produced by the alarm generator 94 sent by alarmloads 96 through an alarm timing selector 9.5 (Fig. 6D) of the kindsimilar to that used in the control timing selector 18. The transmittedpulse;

activates the delay generator 70 (Fig. 6H) used previously and causesthe reorganization process to commence. However, corrective circuitry isalso necessary in t e supervisory channel. Otherwise, at the end of [theclearing period, assuming unimpaired reception of the signatureassociated with the timing channel that has failed, the timing controlselector would once again be directed to select the faulty timingchannel. This is provvidcd by disabling the supervisory channel 13 (Fig6A) associated with the defective timing channel 14 through,

the useof a supervisory gate 42. The signal generated ,by the timingalarm passes .through an OR gate 97 and causes the supervisory gate 42to substitute for the incoming signature on the supervisory channel 13 aselfgenerated alarm signature consisting of a sequence of digits largerthan any receivable from a node of the system. The relay contactorsneeded for producing the alarm signature may be of the kind used in thepreset generator 27 (Fig. 6H As a result the minimum signature placed instorage will be other than that connected with the defective timingchannel. Since the supervisory gate alone produces the samereorganization result as the timing alarm generator in combination withthe alarm timing selector, the latter combination is not strictly neededto cope with timing channel failures. Nevertheless, the use of an alarmtiming selector gives a more rapid response to a timing failure thanwould be possible from having the timing alarm generator operate onlyupon the supervisory gate.

In addition to a failure of the timing signal or an increase of thesupervisory signature, it is possible for an incoming signature itselfto fail. This condition is detected by a signature alarm generator 98whose output 'is directed to an OR gate 97 which is also responsive tothe timing alarm generator 94.

The constituent comparators (Fig. 6G) employed for each digit in thecontrol circuit may be of the relay 'variety shown in Fig. 8.

Such a comparator results from combining simple relays, each having apivoted tongue normally against a back contact, but displaceable againstJ- front contact in response to a signal applied the scanner.

'14 aligned in parallel. The tongues of the first compo nents. of thestorage relays are tied together by an output lead .56, while thetongues of the third components are tied together by a command lead 55.The tongue of each incoming relay, except the first SZ-afwhich isgrounded, is connected to the tongue of the second component of astorage relay in an adjoining pair. When the digits being compared areequal, there is a continuous current path that extends through thesecond component of each storage relay, and an output signal appears onthe equivalence lead 54 of the'comparator. For example, if digit Dincoming and D in storage are both equal to 3, X,, Y,,, X and Y areenergized since the binary equivalent of '3 is 11. Consequently, currentsupplied by the equivalence lead bias battery V-54';is able to flowsuccessively through the front contactsof relay 52-a, of the secondcomponent of relay -53-a, of relay 52-b, and of the second component ofrelay 53-h, the tongues of these relays having moved from theirpositions normally occupied by virtue of the signals applied to theirassociated windings. When the compared digits are unequal, only the casewhere that incoming is less than that in storage is of interest. Then atleast one of the storage relays will be energized, while its pairedincoming relay will not be, with the result that at some stage of thecomparator a completed circuit will be efiected through the back contactof an' incoming relay 52 and thence through the front contact of a thirdcomponent of a storage relay 53 causing the signal to appear on thecommand lead 55. For example, if digit D incoming is l and digit D instorage is '3, in a possible implementation of the comparator relays53-a, 53-h and 52-b are'energized. Current supplied by the command leadbias battery V-55 is able to pass successively through the back contactof incoming relay 52-a andthe front contact of the third component ofthe storage relay 53-41. The fact that relays 52-1) and 53-b are alsoenergized is immaterial since the path formed by them is interrupted atrelay 52-a. The equivalence and command leads 54 and 55 convey signalspresent on them to relays which act in turn to operate AND and OR gates63, 64, and 65 in Fig. 66 the control circuit.

The control circuit for efifecting system reorganization as hereindiscussed has relied upon the employment of relay switches throughout.It is apparent that the necessary circuit components could be wholly orpartly electronic as, for example, in the case of the scanner whichcould employ a ring counter constructed from vacuum tube or solid stateelements. Furthermore, instead of having the signatures handled in theirbinary form, the reception converter could employ a decoder to translateeach digit into a voltage level dependent upon its value. Varioustechniques are possible in handling the signature identifying aparticular node. It may be used in its entirety to direct the controltiming selector; it maybe stored only in part in the register tofacilitate comparison with incoming signatures; or .it may be partlyused to augment incoming signatures at Additionally, .other codingschemes and modes of identifying digits will occur to those skilled inthe art.

What is claimed is: I

1. In a system of interconnected units for carrying out preassignedoperations in a fashion co-ordinated through the distribution among themof primary synchronizing information, said primary synchronizinginformation normally originating with a preassigned unit designated aprimary master, similar control circuits located in the several unitsand responsive to the impaired reception of said primary synchronizinginformation for reorganizing said system to accept, unambiguously,alternative synchronizing information, each of which circuits comprisesmeans for producing and registering a signature unique to the controlcircuit and unambiguously

